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In many electronic systems, especially those which include processing systems with integrated memory, it is important to be able to test the operation of the integrated memory. For example, it is desirable to test the integrity of a memory chip in the system before it is sold to a customer or incorporated into a product. This is because if the memory is defective, it may render the product useless. Also, if the memory is defective, it may be difficult and expensive to repair.
When testing memory using logic signals, it is possible to test each bit of a memory array in parallel. For example, using 1-of-N decoding and a number of spare rows and columns, it is possible to test every word of a memory array simultaneously. However, these tests can only test for defects in memory that are addressed by the spare rows and columns and cannot be applied to a memory system where the location of the be359ba680
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